Difference between revisions of "SC System"
From NaplesPU Documentation
(Created page with "The nu+ single core system is defined in the ''nuplus_system.sv'' module, under src/sc/system folder. The single core version instantiates the following modules: # nu+ core:...") |
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# core interface: core_interface module, connects the nu+ core and the cache-controller for the single core version, module sc_cache_controller | # core interface: core_interface module, connects the nu+ core and the cache-controller for the single core version, module sc_cache_controller | ||
# cache controller: sc_cache_controller module, the cache controller for the single core version of the nu+ architecture, described in [[SC_CC|Cache Controller]] | # cache controller: sc_cache_controller module, the cache controller for the single core version of the nu+ architecture, described in [[SC_CC|Cache Controller]] | ||
| − | # synchronization core: synchronization_core module, acts as the synchronization master allowing thread synchronization through barriers. The module is the same | + | # system bus: mux_multimaster module, shared multi-master bus. It allows both the core and the host-interface to concurrently access the main memory and custom devices |
| + | # test device: io_device_test module, an example of a memory mapped custom device in the nu+ system | ||
| + | # synchronization core: synchronization_core module, acts as the synchronization master allowing thread synchronization through barriers. The module is the same as the many core version, although it requires minor adjustments: | ||
assign network_available = 1'b1; | assign network_available = 1'b1; | ||
assign ni_account_mess_valid = c2n_account_valid; | assign ni_account_mess_valid = c2n_account_valid; | ||
| − | Since the single core version of the system has no network, the network | + | Since the single core version of the system has no network, the network availability input port has to be constantly high. |
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Revision as of 19:55, 31 March 2019
The nu+ single core system is defined in the nuplus_system.sv module, under src/sc/system folder. The single core version instantiates the following modules:
- nu+ core: module nuplus_core (described in nu+ core architecture)
- item interface: nuplus_item_interface module, allows host-device communication and performance info fetching
- transaction logger: nuplus_core_logger module, which logs both incoming responses from the main memory and issued requests from the core to the memory. This module stores up to CORE_LOG_SIZE (default 512) for the core issued transactions, and MEM_LOG_SIZE (default 512)
- core interface: core_interface module, connects the nu+ core and the cache-controller for the single core version, module sc_cache_controller
- cache controller: sc_cache_controller module, the cache controller for the single core version of the nu+ architecture, described in Cache Controller
- system bus: mux_multimaster module, shared multi-master bus. It allows both the core and the host-interface to concurrently access the main memory and custom devices
- test device: io_device_test module, an example of a memory mapped custom device in the nu+ system
- synchronization core: synchronization_core module, acts as the synchronization master allowing thread synchronization through barriers. The module is the same as the many core version, although it requires minor adjustments:
assign network_available = 1'b1; assign ni_account_mess_valid = c2n_account_valid;
Since the single core version of the system has no network, the network availability input port has to be constantly high.
