Coherence

Nu+ cores can be arranged as a many-core architecture based upon a shared-memory subsystem. With the shared-memory model, communication occurs implicitly through the loading and storing of data and the accessing of instructions. Logically, all processors access the same shared memory, allowing each to see the most up-to-date data. Practically speaking, memory hierarchies use caches to improve the performance of shared memory systems. These cache hierarchies reduce the latency to access data but complicate the logical, unified view of memory held in the shared memory paradigm. As a result, cache coherence protocols are designed to maintain a coherent view of memory for all processors in the presence of multiple cached copies of data. Therefore, it is the cache coherence protocol that governs what communication is necessary in a shared memory multiprocessor.
Two key characteristics of a shared memory multiprocessor shape its demands on the interconnect; the cache coherence protocol that makes sure nodes receive the correct up-to-date copy of a cache line, and the cache hierarchy.

Cache Coherence Protocol

Nu+ many-core architecture uses a directory protocol to enforce coherence; directory protocols do not rely on any implicit network ordering and can be mapped to an arbitrary topology. Directory protocols rely on point-to-point messages rather than broadcasts as in snooping protocols; this reduction in coherence messages allows this class of protocols to provide greater scalability. Rather than broadcast to all cores, the directory contains information about which cores have the cache block. A single core receives the read request from the directory resulting in lower bandwidth requirements.

Directories maintain information about the current sharers of a cache line in the system as well as coherence state information. By maintaining a sharing list, directory protocols eliminate the need to broadcast invalidation requests to the entire system. Addresses are interleaved across directory nodes; each address is assigned a home node, which is responsible for ordering and handling all coherence requests to that address; hence there isn't a single directory but instead a distributed one across all tiles of the NoC.

Furthermore the directory is inclusive; this means that directory holds entries for a superset of all blocks cached on the chip. In this way it is possible to design directory caches that are more cost-effective by exploiting the observation that only cache directory states for blocks that are being cached on the chip are needed. A miss in the inclusive directory cache indicates that the block is in state N. Because the directory mirrors the contents of the LLC, the entire directory cache is embedded in the LLC simply by adding extra bits to each block in the LLC. Unfortunately, LLC inclusion has several drawbacks. First, for the shared caches in our system model, it is generally necessary to send special recall requests to invalidate blocks from the L1 caches when replacing a block in the LLC. More importantly, LLC inclusion requires maintaining redundant copies of cache blocks that are in upper-level caches.

Cache Hierarchy

Caches are employed to reduce the memory latency of requests. They also serve as filters for the traffic that needs to be placed on the interconnect. Each of the tiles in Nu+ many-core architecture contain a bank of shared L2 cache. With a shared L2 cache, a L1 miss will be sent to a L2 bank determined by the miss address (not necessarily the local L2 bank), where it could hit in the L2 bank or miss and be sent off-chip to access main memory.

Shared caches represent a more effective use of storage as there is no replication of cache lines. However, L1 cache miss incur additional latency to request data from a different tile. Shared caches place more pressure on the interconnection network as L1 misses also go onto the network, but through more effective use of storage may reduce pressure on the off-chip bandwidth to memory. With shared caches, more requests will travel to remote nodes for data. Using this configuration the on-chip network must attach to both the L1s and the L2.

Memory controllers are placed as individual nodes on the interconnection network; with this design, memory controllers do not have to share injection/ejection bandwidth to/from the network with cache traffic. In this way traffic is more isolated; the memory controller has access to the full amount of injection bandwidth.

Una particolare attenzione è stata posta sul disaccoppiamento tra la gestione della coerenza e la gestione del dato all'interno del datapath del core. I core non hanno coscienza del protocollo di coerenza, ma hanno solo una visione dei privilegi sui dati. I dati ed i privilegi sono opportunamente manipolati dall'infrastruttura di coerenza. Il protocollo di coerenza può essere sostanzialmente intercambiabile con altri.

Lo sviluppo dell'architettura di coerenza si basa su tre attori principali:

• Load Store Unit: contiene la cache L1 e si occupa di gestire la schedulazione delle richieste tra i vari thread del core.
• Cache Controller: gestisce la coerenza dei blocchi della cache livello 1, comunicando direttamente con la Load Store unit ed inviando/ricevendo messaggi di coerenza verso/da altri controllori attraverso una network interface.
• Directory Controller: contiene e gestisce direttamente la coerenza dei blocchi della cache livello 2 e della cache della directory distribuita, comunicando con gli altri controllori tramite lo scambio di messaggi sulla network attraverso l'opportuna interfaccia.

La Load Store unit ed il Cache controller si trovano all'interno del core nu+, mentre il Directory controller è istanziato all'esterno del core nu+ entro la tile.

L1 cache

Lo sviluppo architetturale della cache è basato su tali ipotesi restrittive:

• Se un thread all'interno di un core scatena un cache miss, tale thread è arrestato finchè il controllore di coerenza della cache L1 garantisce le condizioni per poter proseguire l'esecuzione dettate dal protocollo. Tale scelta semplifica l'architettura ed evidenzia la capacità del core di poter eseguire altri calcoli da parte di altri thread attivi, nascondendo le latenze del protocollo di coerenza.
• Non è supportato il merging delle richieste di coerenza da parte di un core.
• E' possibile istanziare solo reti N x N, dove N è una potenza di 2; questo implica l'introduzione di tile vuote che non hanno a disposizione una porzione della cache L2 e directory, a differenza delle tile per il controllo della memoria principale e per la comunicazione con l'host.

Prendendo in considerazione tali assunti e ricordando l'indipendenza tra datapath e controllo di coerenza, si descrivono i due attori principali, cioè L1 cache controller e Load/store unit.

Load/Store unit

This unit is described in the dedicated load/store unit page.

L1 cache controller

This unit is described in the dedicated L1 cache controller page.

L2 and directory cache

This unit is described in the dedicated L2 and Directory cache controller page.