MC System
From NaplesPU Documentation
The many-core version of the project provides different type of tiles, although all share the same network- and coherence-related components. On the networking side, a generic tile of the system features a Network Interface module and a hardware Router, both described in Network architecture section.
The nu+ many-core features a shared-memory system, each nu+ core has a private L1 data cache, while the L2 cache is spread all over the instantiated tile, along with a Directory Controller modules which handles and stores coherence information for cached memory lines. This component is further described in Coherence architecture section.
Contents
NUPLUS tile
The NUPLUS tile
MC tile
H2C tile
NONE tile
HT tile
Described in Heterogeneous Tile section.
