Basic comps
From NaplesPU Documentation
The following section describes all the basic components used in the design of the system. Such components are located in the src/common folder and due to their extensive use we dedicate this section to
Memory Banks
Two components are mainly used as memory banks:
- memory_bank_1r1w
- memory_bank_2r1w
They both are memory elements (often mapped as a BRAM in Vivado).
Their interfaces are similar, although the memory_bank_2r1w has an extra reading port, obtained allocating two memory_bank_1r1w modules with their writing port connected together. In this way, each write operation is propagated to both elements, and the two memories are aligned in their content, thus the same reading operation performed on both fetches the same value.
