Difference between revisions of "The NaplesPU Hardware architecture"
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[[File:Manycore.png|800px|nu+ manycore architecture]] | [[File:Manycore.png|800px|nu+ manycore architecture]] | ||
| − | User design can set an high number of parameter for every need, such as: | + | User design can set an high number of parameter for every need, such as: * NoC topology and Tile number. |
| − | * NoC topology and Tile number. | ||
* Threads per core number. Each thread has a different PC, so one core can executes as many program as many threads it has. | * Threads per core number. Each thread has a different PC, so one core can executes as many program as many threads it has. | ||
* Hardware lanes per thread. Each thread can be a vector operation (here called hardware lane). | * Hardware lanes per thread. Each thread can be a vector operation (here called hardware lane). | ||
Revision as of 10:29, 23 September 2017
The nu+ manycore is a parametrizable regular mesh Network on Chip (NoC) of configurable tile, developed by CeRICT in the framework of the MANGO FETHPC project. The main objective of \nuplus is to enable resource-efficient HPC based on special-purpose customized hardware. Our aim is to build an application-driven architecture to achieve the best hardware/software configuration for any data-parallel kernel. Specialized data-parallel accelerators have been known to provide higher efficiency than general-purpose processors for codes with significant amounts of regular data-level parallelism (DLP). However every parallel kernel has its own ideal configuration.
Each nu+ tile has the same basic components, it provides a configrable GPU-like open-source softcore meant to be used as a configurable FPGA overlay. This HPC-oriented accelerator merges the SIMT paradigm with vector processor model. Futhermore, each tile has a Cache Controller and a Directory Controller, those components handle data coherence between different cores in different tiles.
User design can set an high number of parameter for every need, such as: * NoC topology and Tile number.
- Threads per core number. Each thread has a different PC, so one core can executes as many program as many threads it has.
- Hardware lanes per thread. Each thread can be a vector operation (here called hardware lane).
- Register file size (scalar and vector).
- L1 and L2 cache size and way number.
There are all the hardware main section. Each of them covers important aspects of the hardware.
