Difference between revisions of "Extending NaplesPU for 64-bit support"

Revision as of 11:56, 14 May 2019

nu+ toolchain can be extended to support 64-bit operations. A git branch with full 64-bit support is provided. Consequently, if it is necessary to compile the toolchain supporting this extension, a checkout on llvm-7-64b branch is required.

Changes are related to both frontend and backend.

nu+ Frontend Modifications

nu+ frontend abstracts target informations through the TargetInfo class, extending it in the NuPlusTargetInfo implementation.

Since 64-bit operations require to support double-integer and double-floating-point formats, the following changes and additions are required in the target definition:

 class LLVM_LIBRARY_VISIBILITY NuPlusTargetInfo : public TargetInfo {
   ...
 public:
   NuPlusTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     : TargetInfo(Triple) {
     ...
     resetDataLayout("e-m:e-p:32:32-i64:64:64-i32:32:32-f32:32:32-f64:64:64");
     LongDoubleWidth = 64;
     LongDoubleAlign = 64;
     DoubleWidth = 64;
     DoubleAlign = 64;
     LongWidth = 64;
     LongAlign = 64;
     LongLongWidth = 64;
     LongLongAlign = 64;
   }

nu+ Backend Modifications

This section describes the backend modification to be applied for 64-bit support.

Registers Definition

class NuPlus64GPRReg<bits<16> Enc, string n, list<Register> subregs>
  : NuPlusRegWithSubRegs<Enc, n, subregs> {
  let SubRegIndices = [sub_even, sub_odd];
  let CoveredBySubRegs = 1;
}

  foreach i = 0-28 in {
    def S#!shl(i, 1)#_S#!add(!shl(i, 1), 1) : NuPlus64GPRReg<!shl(i, 1), "s"#!shl(i, 1)#_64,
                 [!cast<NuPlusGPRReg>("S"#!shl(i, 1)),
                  !cast<NuPlusGPRReg>("S"#!add(!shl(i, 1), 1))]>;
  }