Difference between revisions of "NaplesPU.td"
| Line 1: | Line 1: | ||
[[Category:Tablegen Files]] | [[Category:Tablegen Files]] | ||
| − | + | //===-- NuPlus.td - Describe the NuPlus Target Machine -------*- tablegen -*-===// | |
| + | // | ||
| + | // The LLVM Compiler Infrastructure | ||
| + | // | ||
| + | // This file is distributed under the University of Illinois Open Source | ||
| + | // License. See LICENSE.TXT for details. | ||
| + | // | ||
| + | //===----------------------------------------------------------------------===// | ||
| + | // | ||
| + | // | ||
| + | //===----------------------------------------------------------------------===// | ||
| − | + | //===----------------------------------------------------------------------===// | |
| + | // Target-independent interfaces which we are implementing | ||
| + | //===----------------------------------------------------------------------===// | ||
| + | |||
| + | include "llvm/Target/Target.td" | ||
| + | |||
| + | //===----------------------------------------------------------------------===// | ||
| + | // Register File, Calling Conv, Instruction Descriptions | ||
| + | //===----------------------------------------------------------------------===// | ||
include "NuPlusRegisterInfo.td" | include "NuPlusRegisterInfo.td" | ||
| Line 10: | Line 28: | ||
def NuPlusInstrInfo : InstrInfo; | def NuPlusInstrInfo : InstrInfo; | ||
| − | |||
def NuPlusAsmParser : AsmParser { | def NuPlusAsmParser : AsmParser { | ||
| − | |||
| − | |||
bit ShouldEmitMatchRegisterName = 1; | bit ShouldEmitMatchRegisterName = 1; | ||
} | } | ||
| − | // | + | //===----------------------------------------------------------------------===// |
| + | // Declare the target which we are implementing | ||
| + | //===----------------------------------------------------------------------===// | ||
| + | |||
def NuPlusAsmWriter : AsmWriter { | def NuPlusAsmWriter : AsmWriter { | ||
string AsmWriterClassName = "InstPrinter"; | string AsmWriterClassName = "InstPrinter"; | ||
| − | |||
bit isMCAsmWriter = 1; | bit isMCAsmWriter = 1; | ||
} | } | ||
Revision as of 12:54, 5 April 2019
//===-- NuPlus.td - Describe the NuPlus Target Machine -------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// // Target-independent interfaces which we are implementing //===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===//
include "NuPlusRegisterInfo.td" include "NuPlusCallingConv.td" include "NuPlusInstrInfo.td"
def NuPlusInstrInfo : InstrInfo;
def NuPlusAsmParser : AsmParser {
bit ShouldEmitMatchRegisterName = 1;
}
//===----------------------------------------------------------------------===// // Declare the target which we are implementing //===----------------------------------------------------------------------===//
def NuPlusAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter"; bit isMCAsmWriter = 1;
}
def : Processor<"nuplus", NoItineraries, []>;
def NuPlus : Target {
// Pull in Instruction Info: let InstructionSet = NuPlusInstrInfo; let AssemblyParsers = [NuPlusAsmParser]; let AssemblyWriters = [NuPlusAsmWriter];
} </syntaxhighlight>
