Difference between revisions of "Single Core Cache Controller"
From NaplesPU Documentation
(Created page with "This module is the L1 cache controller allocated in the nu+ core.") |
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| − | This module is the L1 cache controller allocated in the nu+ core. | + | This module is the L1 cache controller allocated in the nu+ core. It doesn't link directly to LDST unit, but there is a component that it filter all request from LDST: core interface. This component is needed because decouples a service speed of cache controller and service speed of LDST units, in fact cache controller can manage one request at a time but there are more than one LDST units so they can send more than one request at a time. Core interface receive a request from the LDST unit (all the event concerned to the memory: miss, flush, evict) and store it in one of four queue. |
Revision as of 17:16, 4 April 2019
This module is the L1 cache controller allocated in the nu+ core. It doesn't link directly to LDST unit, but there is a component that it filter all request from LDST: core interface. This component is needed because decouples a service speed of cache controller and service speed of LDST units, in fact cache controller can manage one request at a time but there are more than one LDST units so they can send more than one request at a time. Core interface receive a request from the LDST unit (all the event concerned to the memory: miss, flush, evict) and store it in one of four queue.
