Difference between revisions of "NaplesPU Libraries"
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| − | + | NaplesPU is provided with different kind of libraries that are contained in the libs/ folder. | |
== libc == | == libc == | ||
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*ISD::SDIV | *ISD::SDIV | ||
*ISD::SREM | *ISD::SREM | ||
| − | This happends because the above nodes are set to ''Expand'' inside the [[ | + | This happends because the setOperationAction for the above nodes are set to ''Expand'' inside the [[NaplesPUISelLowering_class | NaplesPUISelLowering.cpp]] file. |
| − | == crt0 == | + | == isr== |
| + | This folder contains the NaplesPU Interrupt Service Routines (ISRs). In the current version we have just a single isr, i.e. isr0, which implements an endless loop. | ||
| + | |||
| + | == vectors.s == | ||
| + | This assembler file contains the Interrupt Vector Jump Table. Jump operations to the different ISRs are stored in consecutive 32-bit locations. Since, in the current version we have just a single isr, there is only one jump operations. | ||
| + | |||
| + | == crt0.s == | ||
| + | This file contains a set of execution startup routines that performs any initialization work required before calling the program's main function. The main steps are: | ||
| + | # Loading the stack/frame pointers from the stack table that is located at the end of the file. The stack table is filled with the addresses of the different stacks that are defined inside the [[LinkerScript | linker script]]. The current version supports eight threads for each core. The offset inside the stack_table is calculated as i*32+j*4, where ''i'' is the core ID and j is the thread ID. In case of an higher number of threads, it is required to change both the crt0.o and the [[LinkerScript | linker script]]. | ||
| + | # Thread 0 of Core 0 performs constructor startup required for the initialization of C/C++ objects. This is done by calling the functions that are located inside the .init_array section. | ||
| + | # Threads 0 of each core performs scratchpad preload initialization. This is done using first vector loads/stores, then 64-bit scalar loads/stores and finally 32-bit scalar loads/stores. | ||
| + | # The argc and argv arguments are put inside the s0 and s1 registers according to the NaplesPU [[NaplesPUCallingConv.td | calling convention]]. | ||
| + | # All hardware lanes are enabled by default. | ||
Latest revision as of 16:22, 21 June 2019
NaplesPU is provided with different kind of libraries that are contained in the libs/ folder.
Contents
libc
We implemented our custom version of the following standard C libraries:
- ctype
- math
- stdlib
- string
Note that these libraries are not fully developed and, hence, some functions may be missing. In particular, dynamic memory management (calloc, free, malloc, realloc) and environment (abort, atexit, at_quick_exit, exit, getenv, quick_exit, system) functions are not implemented. In addition, we redefined the stdint.h header file in order to provide a set of typedefs that specify vector types.
During compilation, these libraries are archived together into a single file, i.e. libc.a, using the llvm-ar archiver.
libcompiler
This folder contains the libraries that are required by the compiler to handle some arithmetic operations that are not legal in the target architecture. In particular, we implemented the following libraries:
- divdi3.c: signed 64-bit integer division
- divsi3.c: signed 32-bit integer division
- moddi3.c: signed 64-bit integer modulus
- modsi3.c: signed 32-bit integer modulus
- udivdi3.c: unsigned 64-bit integer division
- udivsi3.c: unsigned 32-bit integer division
- umoddi3.c: unsigned 64-bit integer modulus
- umodsi3.c: unsigned 32-bit integer modulus
A proper lib call is generated when lowering the following node types:
- ISD::UDIV
- ISD::UREM
- ISD::SDIV
- ISD::SREM
This happends because the setOperationAction for the above nodes are set to Expand inside the NaplesPUISelLowering.cpp file.
isr
This folder contains the NaplesPU Interrupt Service Routines (ISRs). In the current version we have just a single isr, i.e. isr0, which implements an endless loop.
vectors.s
This assembler file contains the Interrupt Vector Jump Table. Jump operations to the different ISRs are stored in consecutive 32-bit locations. Since, in the current version we have just a single isr, there is only one jump operations.
crt0.s
This file contains a set of execution startup routines that performs any initialization work required before calling the program's main function. The main steps are:
- Loading the stack/frame pointers from the stack table that is located at the end of the file. The stack table is filled with the addresses of the different stacks that are defined inside the linker script. The current version supports eight threads for each core. The offset inside the stack_table is calculated as i*32+j*4, where i is the core ID and j is the thread ID. In case of an higher number of threads, it is required to change both the crt0.o and the linker script.
- Thread 0 of Core 0 performs constructor startup required for the initialization of C/C++ objects. This is done by calling the functions that are located inside the .init_array section.
- Threads 0 of each core performs scratchpad preload initialization. This is done using first vector loads/stores, then 64-bit scalar loads/stores and finally 32-bit scalar loads/stores.
- The argc and argv arguments are put inside the s0 and s1 registers according to the NaplesPU calling convention.
- All hardware lanes are enabled by default.
