Difference between revisions of "NaplesPURegisterInfo.td"

//===-- NaplesPURegisterInfo.td - NaplesPU Register defs ---------*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
//  Declarations that describe the NaplesPU register file
//===----------------------------------------------------------------------===//

let Namespace = "NaplesPU" in {
def sub_even : SubRegIndex<32>;
def sub_odd  : SubRegIndex<32, 32>;
}

class NaplesPUReg<bits<16> Enc, string n> : Register<n> {
  let HWEncoding = Enc;
  let Namespace = "NaplesPU";
}

class NaplesPURegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
  : RegisterWithSubRegs<n, subregs> {
  let HWEncoding = Enc;
  let Namespace = "NaplesPU";
}

// NaplesPU 32-bit registers
class NaplesPUGPRReg<bits<16> Enc, string n> : NaplesPUReg<Enc, n>;

//===----------------------------------------------------------------------===//
//  Registers
//===----------------------------------------------------------------------===//


  // General Purpose scalar registers
  foreach i = 0-57 in {
    def S#i : NaplesPUGPRReg<i, "s"#i>, DwarfRegNum<[i]>;
  }

  //trap register
  def TR_REG : NaplesPUGPRReg<58, "tr">, DwarfRegNum<[58]>;
  //mask register
  def MR_REG : NaplesPUGPRReg<59, "rm">, DwarfRegNum<[59]>;
  //frame pointer
  def FP_REG : NaplesPUGPRReg<60, "fp">, DwarfRegNum<[60]>;
  //stack pointer
  def SP_REG : NaplesPUGPRReg<61, "sp">, DwarfRegNum<[61]>;
  //return address
  def RA_REG : NaplesPUGPRReg<62, "ra">, DwarfRegNum<[62]>;
  //PC
  def PC_REG : NaplesPUGPRReg<63, "pc">, DwarfRegNum<[63]>;

  // General Purpose vectorial registers
  foreach i = 0-63 in {
    def V#i : NaplesPUGPRReg<i, "v"#i>, DwarfRegNum<[!add(i, 64)]>;
  }

//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//

// This register class should not be used to hold i64/f64 values, use the GPR64
// register class for that. The i64/f64 type is included here to allow i64/f64
// patterns using the instructions.
def GPR32 : RegisterClass<"NaplesPU", [i32, f32], 32, (add (sequence "S%u", 0, 57),
  TR_REG, MR_REG, FP_REG, SP_REG, RA_REG, PC_REG)>

def VR512W : RegisterClass<"NaplesPU", [v16i32, v16f32, v16i8, v16i16], 512, (sequence "V%u", 0, 63)>;