Difference between revisions of "MC System"
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== NUPLUS tile == | == NUPLUS tile == | ||
| − | The NUPLUS tile mainly equips a nu+ GPGPU core, described in [[Core|Nu+ GPGPU core]] section, and components used to interface the core with both networking and coherence systems. The following figure depicts | + | The NUPLUS tile mainly equips a nu+ GPGPU core, described in [[Core|Nu+ GPGPU core]] section, and components used to interface the core with both networking and coherence systems. The following figure depicts a block view of the NUPLUS tile: |
[[File:NU.jpg|900px]] | [[File:NU.jpg|900px]] | ||
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| + | The tile implements a '''Cache controller''', called ''l1d_cache'', which interfaces the core to the memory system. The Cache controller exploits three Network interface virtual channels dedicated to the coherence system (ID 0 to 2), providing an abstracted view of the coherence to the core. For further details of the module and of the coherence system refer to [[Coherence|Coherence architecture]] section. | ||
== MC tile == | == MC tile == | ||
Revision as of 12:26, 17 May 2019
The many-core version of the project provides different type of tiles, although all share the same network- and coherence-related components. On the networking side, a generic tile of the system features a Network Interface module and a hardware Router, both described in Network architecture section.
The nu+ many-core features a shared-memory system, each nu+ core has a private L1 data cache, while the L2 cache is spread all over the instantiated tile along with a Directory Controller module which handles and stores coherence information for cached memory lines. This component is further described in Coherence architecture section.
Contents
NUPLUS tile
The NUPLUS tile mainly equips a nu+ GPGPU core, described in Nu+ GPGPU core section, and components used to interface the core with both networking and coherence systems. The following figure depicts a block view of the NUPLUS tile:
The tile implements a Cache controller, called l1d_cache, which interfaces the core to the memory system. The Cache controller exploits three Network interface virtual channels dedicated to the coherence system (ID 0 to 2), providing an abstracted view of the coherence to the core. For further details of the module and of the coherence system refer to Coherence architecture section.
MC tile
H2C tile
NONE tile
HT tile
Described in Heterogeneous Tile section.
