Difference between revisions of "Basic comps"
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== Memory Banks == | == Memory Banks == | ||
Two components are mainly used as memory banks: | Two components are mainly used as memory banks: | ||
| − | # memory_bank_1r1w | + | # memory_bank_1r1w: 1 Read port and 1 Write port. |
| − | # memory_bank_2r1w | + | # memory_bank_2r1w: 2 Read ports and 1 Write port. |
| − | They both are memory elements (often mapped as a BRAM in Vivado) | + | They both are memory elements (often mapped as a BRAM in Vivado), the first provides a simple interface and it is highly parametrizable: |
| + | parameter SIZE = 1024, | ||
| + | parameter ADDR_WIDTH = $clog2( SIZE ), | ||
| + | parameter COL_WIDTH = 8, | ||
| + | parameter NB_COL = 4, | ||
| − | + | The reading interface is reported in the following snippet code, when the address is ready, and the enable is high, the SRAM produces on the output bus the requested data the next clock cycle. | |
| + | input logic read_enable, | ||
| + | input logic [ADDR_WIDTH - 1:0] read_address, | ||
| + | output logic [NB_COL*COL_WIDTH - 1:0] read_data | ||
| + | |||
| + | Similarly, the writing interface is reported below. When the data to store and the address are ready, and the enable is set, the SRAM stores the incoming data in the selected address. | ||
| + | input logic [NB_COL - 1:0] write_enable, | ||
| + | input logic [ADDR_WIDTH - 1:0] write_address, | ||
| + | input logic [NB_COL*COL_WIDTH - 1:0] write_data, | ||
| + | |||
| + | In case of concurrent write and read on the address, the behaviour of the SRAM depends on the mode selected on its parameters: | ||
| + | parameter WRITE_FIRST = "TRUE" | ||
| + | |||
| + | If "write_first" is enabled (true), the SRAM first stores the data in the memory then forwards the data just stored on the output signal. The other functionality mode is "read_first" (parameter WRITE_TRUE set to false), in this case, the module first fetch the old data from the memory and outputs it on the reading output signal, then stores into the memory the new data from the interface. | ||
| + | |||
| + | |||
| + | The second module (memory_bank_2r1w) provides a similar interface, although the memory_bank_2r1w has an extra reading port, obtained allocating two memory_bank_1r1w modules with their writing port connected together. In this way, each write operation is propagated to both elements, and the two memories are aligned in their content, thus the same reading operation performed on both fetches the same value. | ||
Revision as of 14:35, 27 March 2019
The following section describes all the basic components used in the design of the system. Such components are located in the src/common folder and due to their extensive use we dedicate this section to
Memory Banks
Two components are mainly used as memory banks:
- memory_bank_1r1w: 1 Read port and 1 Write port.
- memory_bank_2r1w: 2 Read ports and 1 Write port.
They both are memory elements (often mapped as a BRAM in Vivado), the first provides a simple interface and it is highly parametrizable:
parameter SIZE = 1024, parameter ADDR_WIDTH = $clog2( SIZE ), parameter COL_WIDTH = 8, parameter NB_COL = 4,
The reading interface is reported in the following snippet code, when the address is ready, and the enable is high, the SRAM produces on the output bus the requested data the next clock cycle.
input logic read_enable, input logic [ADDR_WIDTH - 1:0] read_address, output logic [NB_COL*COL_WIDTH - 1:0] read_data
Similarly, the writing interface is reported below. When the data to store and the address are ready, and the enable is set, the SRAM stores the incoming data in the selected address.
input logic [NB_COL - 1:0] write_enable, input logic [ADDR_WIDTH - 1:0] write_address, input logic [NB_COL*COL_WIDTH - 1:0] write_data,
In case of concurrent write and read on the address, the behaviour of the SRAM depends on the mode selected on its parameters:
parameter WRITE_FIRST = "TRUE"
If "write_first" is enabled (true), the SRAM first stores the data in the memory then forwards the data just stored on the output signal. The other functionality mode is "read_first" (parameter WRITE_TRUE set to false), in this case, the module first fetch the old data from the memory and outputs it on the reading output signal, then stores into the memory the new data from the interface.
The second module (memory_bank_2r1w) provides a similar interface, although the memory_bank_2r1w has an extra reading port, obtained allocating two memory_bank_1r1w modules with their writing port connected together. In this way, each write operation is propagated to both elements, and the two memories are aligned in their content, thus the same reading operation performed on both fetches the same value.
