Difference between revisions of "Include"
Line 13: | Line 13: | ||
`define FP_REG ( `REGISTER_NUMBER - 4 ) | `define FP_REG ( `REGISTER_NUMBER - 4 ) | ||
`define MASK_REG ( `REGISTER_NUMBER - 5 ) | `define MASK_REG ( `REGISTER_NUMBER - 5 ) | ||
+ | |||
+ | and opcode definitions and instruction decoded-related data structure definitions: | ||
+ | |||
+ | NOT = `OP_CODE_WIDTH'b000000, | ||
+ | OR = `OP_CODE_WIDTH'b000001, | ||
+ | AND = `OP_CODE_WIDTH'b000010, | ||
+ | XOR = `OP_CODE_WIDTH'b000011, | ||
== User Defines == | == User Defines == |
Revision as of 15:20, 26 March 2019
Nu+ Defines
The Nu+ Define incude file (nuplus_defines.sv) stores global define at core level. Parameters, such as number of hardware lanes, number of register per register file, or memory address width, are defined in this file:
`define HW_LANE 16 `define ADDRESS_SIZE 32 `define REGISTER_NUMBER 64
along with information on special purpose registers:
`define PC_REG ( `REGISTER_NUMBER - 1 ) `define RA_REG ( `REGISTER_NUMBER - 2 ) `define SP_REG ( `REGISTER_NUMBER - 3 ) `define FP_REG ( `REGISTER_NUMBER - 4 ) `define MASK_REG ( `REGISTER_NUMBER - 5 )
and opcode definitions and instruction decoded-related data structure definitions:
NOT = `OP_CODE_WIDTH'b000000, OR = `OP_CODE_WIDTH'b000001, AND = `OP_CODE_WIDTH'b000010, XOR = `OP_CODE_WIDTH'b000011,
User Defines
The User Defines include file (nuplus_user_defines.sv) exposes to the final user all the configurable parameters of the architecture. Typically those parameters are bound to be a power of two.
Core-side user defines: all the following are bound to be a power of two
- THREAD_NUMB: number of hardware thread instantiated, default 8.
- USER_ICACHE_SET: number of instruction cache sets, default 32.
- USER_ICACHE_WAY: number of instruction cache sets, default 4.
- USER_DCACHE_SET: number of data cache sets, default 32.
- USER_DCACHE_WAY: number of data cache sets, default 4.
- USER_L2CACHE_SET: number of L2 data cache sets, default 128.
- USER_L2CACHE_WAY: number of L2 data cache sets, default 8.
- NUPLUS_SPM: when defined allocates a scratchpad memory in each nu+ core.
- NUPLUS_FPU: when defined allocates a FPU in each nu+ core.
System-side user defines:
- DIRECTORY_BARRIER: when defined the manycore system supports a distributed directory mechanism spread over all tiles. Otherwise, it allocates a single centralized directory. The single-core version always has a centralized synchronization master.
- CENTRAL_SYNCH_ID: Centralized directory ID, used only when DIRECTORY_BARRIER is undefined.
- NoC_X_WIDTH: Network-on-Chip mesh x dimension width, default value 2, must be power of 2.
- NoC_Y_WIDTH: Network-on-Chip mesh x dimension width, default value 2, must be power of 2.
- TILE_MEMORY_ID: Memory Tile ID.
- TILE_H2C_ID: Host interface Tile ID.
- TILE_NUPLUS: number of tile with a nu+ core.
- IO_MAP_BASE_ADDR: base address of the non-coherent memory space dedicated for IO devices, default value 0xFF00_0000.
- IO_MAP_SIZE: width of the non-coherent memory space dedicated for IO devices, default value 0x00FF_FF00.
Furthermore, DISPLAY variables are defined, all commented by default. When a DISPLAY variable is active, it generates a file, under a folder named after the selected kernel. Each DISPLAY variable logs a defined kind of transaction, namely:
* DISPLAY_MEMORY: logs on file the memory state at the end of the kernel execution. * DISPLAY_MEMORY_TRANS: logs on file all requests to the main memory. * DISPLAY_INT: logs every integer operation in the integer pipeline, and their results. * DISPLAY_CORE: enables log from the core (file display_core.txt). * DISPLAY_ISSUE: logs all scheduled instructions, and tracks the scheduled PC and the issued Thread, when DISPLAY_CORE is defined. * DISPLAY_INT: logs all results from the integer module, when DISPLAY_CORE is defined. * DISPLAY_WB: logs all results from the writeback module, when DISPLAY_CORE is defined. * DISPLAY_LDST: enables logging into the load/store unit (file display_ldst.txt). * DISPLAY_CACHE_CONTROLLER: logs memory transactions between Load/Store unit and the main memory. * DISPLAY_SYNCH_CORE: logs synchronization requests within the core. * DISPLAY_BARRIER_CORE: logs synchronization releases from the Synchronization master. * DISPLAY_COHERENCE: logs all coherence transactions among CCs, DCs and MC. * DISPLAY_THREAD_STATUS: displays all active threads status and trap reason.
These variables selectively enable the logging of a specific feature. For each define, a log file is typically created in nuplus/simulationlog/<name_of_the_kernel>/display_<name>. DISPLAY_SIMULATION_LOG variable has to be always defined in the simulation flow, this also displays architectural information on the tcl shell.