Month: June 2019

The Naples Processing Unit, dubbed NaplesPU or NPU, is a comprehensive open-source manycore accelerator, encompassing all the architecture layers from the compute core up to the on-chip interconnect, the coherence memory hierarchy, and the compilation toolchain.

Entirely written in System Verilog HDL, NaplesPU exploits the three forms of parallelism that you normally find in modern compute architectures, particularly in heterogeneous accelerators such as GPU devices: vector parallelism, hardware multithreading, and manycore organization. Equipped with a complete LLVM-based compiler targeting the NaplesPU vector ISA, our open-source project will let you experiment with all of the flavors of today’s manycore technologies.

These are the key ambitions of the NaplesPU project:

• be a reference open-source project featuring a fully fledged GPU-like processing system,
• provide a configurable and open platform for the design and evaluation of customized accelerators,
• offering free remote access to a powerful emulation platform, under negotiated conditions, in addition to the mere source code,
• become an unparalleled learning resource for students and practitioners who want to put their hands on the internals of a manycore architecture.

The NaplesPU wiki will guide you through the internals of the hardware project and the related LLVM-based toolchain. It is superdetailed and will turn out to be an excellent resource for both delving deeply into the project and learning more about vector processor and manycore architectures!

NaplesPU is not only an open-source project, meaning free access to the code we developed (under the 3-clause BSD licence). We can also provide a physical platform for your architecture exploration! The platform is available as a major outcome of the H2020 MANGO project, and is being maintained with some financial support from the H2020 RECIPE project.

We provide access to two types of FPGA-based resources available for hardware emulation:

• a cluster of sixteen ultra-large Xilinx Virtex 7 FPGA devices (Virtex 7-2000T),
• an advanced Xilinx Alveo U280 card, also providing innovative in-package High-Bandwidth Memory v.2, currently provided by Xilinx in a pre-production Engineering Sample (ES) version.

The NaplesPU code is organized in two repositories, both hosted by the GitHub platform:

NaplesPU hardware code, mostly System Verilog:

https://github.com/AlessandroCilardo/NaplesPU

NaplesPU LLVM-based compilation toolchain:

https://github.com/AlessandroCilardo/NaplesPU-toolchain

The NaplesPU System Verilog code, as well as the custom parts of the NaplesPU toolchain, are covered by the 3-clause BSD license. This type of licenses is classified as permissive, as it imposes minimal restrictions on the use and distribution of the code. As a consequence, you should feel pretty comfortable while reusing the NaplesPU code for your own purposes. In particular, you are not required to distribute the source code in case you incorporate and/or modify NaplesPU in your project. You are just required to keep the BSD license notice and copyright information in the covered source files, if you redistribute them in an open form, or reproduce the notice and copyright information separately in a readable form, if you redistributed binary code.

That should save you most licensing headaches!